1. Field of Invention
The present invention relates to semiconductor memory devices. More particularly, the present invention relates to a layout structure for a dynamic random access memory (DRAM) in which bit line equalization transistors are provided with a bit line equalization voltage.
2. Description of the Related Art
In order to facilitate the fabrication of DRAMs, an effort has been continuously made to decrease the core and peripheral circuit regions provided with the memory cells and bit line sense amplifiers. For example and with reference to FIGS. 1 and 2, a conventional DRAM provided with stack memory cells, which consist of a storage poly and plate poly stacked over a semiconductor substrate, has a large offset between a cell array region 10 and a region 20 comprising bit line equalization transistors. This relationship makes it very difficult to form an active metal contact 21 to electrically connect metal line VBL(M1) and the active region 30 in order to supply a bit line equalization voltage VBL to bit line equalization regions 20 connected to the active region 30. In order to cope with this difficulty, plate poly 22 is extended to the edge of cell array region 10, as shown in FIG. 2, while the bit line transistors are arranged in bit line equalization region 20 and are separated from an edge of plate poly 22 by a space L. Metal contact 21 is then formed between metal line VBL (M1) and active region 30 to supply bit line equalization voltage VBL to the bit line equalization transistors.
However, since there exists a large offset between cell array region 10 and region 20 comprising the bit line equalization transistors, the metal contact 21 between the metal line VBL(M1) and an active n+ region of the bit line equalization transistors is formed at a great distance from cell array region 10. This increases chip size. In fact, metal contact 21 becomes the bottle-neck of the overall metal-active (n+ or p+) contact process in the DRAM fabrication process, thus, increasing the size of the metal-active contact of the other regions so that the minimum distance between the metal-active contact and the gate must be increased in most of the transistors in the peripheral regions. Chip size necessarily increases.
Accordingly, the bit line equalization region 20 is a very critical place to design metal-active contacts in the DRAM. In addition, the metal-active contact between all the bit line equalization transistors and the metal line VBL(M1) supplying bit line equalization voltage VBL to the bit line equalization region 20 generates a contact overlap so as to reduce the metal line space, adversely affecting the metal line bridge margin, for example, the margins between active region 30 and plate poly 22, and active region 30 and the equalization metal line VBL(M1).
The present invention is therefore directed to a layout structure which substantially overcomes one or more of the problems due to the limitations and disadvantages of the related art.
The present invention provides a layout structure for DRAM which secures proper margins for the metal contact and metal line to supply the bit line equalization voltage without increasing the chip size.
In one aspect the present invention provides a layout structure for a semiconductor memory device, including a semiconductor substrate of first conductivity type having a main surface, a plurality of memory cell array regions arranged in a row on the main surface of the semiconductor substrate, a plurality of bit line equalization regions formed on the main surface of the semiconductor substrate lateral to and spaced apart from the plurality of memory cell array regions, such that each one of the plurality of bit line equalization regions defines a column perpendicular to the row, a word line drive region disposed in the row between adjacent memory cell array regions and between columns defined by adjacent bit line equalization regions, an impurity region of second conductivity type formed parallel to the row and between the plurality of cell array regions and the plurality of bit line equalization regions on the main surface of the semiconductor substrate, the impurity region of second conductivity type being electrically coupled to the plurality of bit line equalization regions, a metal line extending over the impurity region of second conductivity type and supplying a bit line equalization voltage to the impurity region of second conductivity type, and a contact that electrically contacts the metal line to the impurity region of second conductivity type and that is disposed lateral to the word line drive region in a columnar direction, so that no contacts are formed directly between the plurality of memory cell array regions and the plurality of bit line equalization regions in the columnar direction.
In another aspect, the present invention provides a layout structure for a semiconductor memory device formed on a semiconductor substrate, including a rectangular memory cell array region having a top edge, a bottom edge, and two lateral edges, wherein the top and bottom edges define a row-wise plane in the surface of the semiconductor substrate, and wherein the lateral edges define a columnar plane in the surface of the semiconductor substrate, a word line drive region proximate the rectangular memory cell array region and disposed within the row-wise plane, a bit line equalization region spaced apart and disposed laterally from the rectangular memory cell array region within the columnar plane, an impurity region formed between the rectangular memory cell array region and the bit line equalization region, and electrically coupled to the bit line equalization region, a metal line supplying a bit line equalization voltage to the impurity region, and a contact that electrically couples the metal line to the impurity region and that is formed lateral to the word line drive region outside the columnar plane, so that no contacts are formed directly between the rectangular memory cell array region and the bit line equalization region in a columnar direction.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.